interleaved memory

An interleaved memory with "n" banks is said to be n-way interleaved.

If the cells are added as floating cells (no interleaved memory) they can also be warm added and removed from the partition.

FRISC got its name from a design that included on-board floating point and interleaved memory.

Memory was spread across 16 interleaved memory banks, each with a 50 ns cycle time, allowing up to four words to be read per cycle.

The processors are connected with non-internally blocking crossbar switch and communicate with each other via global interleaved memory.

In computing, interleaved memory is a design made to compensate for the relatively slow speed of core memory or DRAM.

They will communicate with each other via global interleaved memory (memory that can be written to and read by all threads) in the SRAM.

Early research into interleaved memory was performed at IBM in the 60s and 70s in relation to the IBM 7030 Stretch computer but development went on for decades improving design, flexibility and performance to produce modern implementations.

With interleaved memory, memory addresses are allocated to each memory bank in turn such that in an interleaved system with 2 memory banks (assuming word-addressable memory) if address 32 belongs to bank 0, 33 would belong to bank 1, 34 would belong to bank 0 and so on.