All models are provided with 256 KB of data cache.
The chip doubles instruction cache to 256Kb, the same size as the data cache.
A single read port is used to deliver data to the two banks of data cache.
The data cache is accessed with two 128-bit buses.
The data cache consists of eight banks separated by 32-bit boundaries.
To accommodate these features, the data cache was reduced in size to 8 KB.
The data cache is dual-ported, so two reads or writes can be performed during every cycle.
As a microarchitecture, the 68030 is basically a 68020 core with an additional data cache and a process shrink.
Was it imagining things, or were there faint hints that the data cache had been doctored?
The data cache keeps copies of 64-byte lines of memory.
