To prevent this, every cache controller monitors the bus, listening for broadcasts which may cause it to invalidate its cache line.
All cache controllers monitor the bus.
Integrated low-latency level-2 cache controller, up to 4 MB per cluster.
Instead, the processor has an on-chip cache controller which controls separate external data and instruction caches.
In early designs a cache miss would force the cache controller to stall the processor and wait.
The hard disk is also fast, without the benefit of a cache controller.
It is connected to the cache controller by a 128-bit data path.
Each cache line also has a valid bit and a dirty bit, stored in the cache controller.
Austek produced a number of digital signal processing chips, but their most successful products were cache controllers.
The cache controller and cache tags are on-die.