shift register

The particular configuration of the shift register turned out to be vulnerable to "guess and determine" attacks.

To deserialize the data, a shift register and counter may be employed.

Initially, the 128 key bits are loaded into a shift register.

When invoked by the master, the data is clocked out from the shift register.

The shift register may be initialized with ones instead of zeroes.

The circuit of a 2-bit shift register is shown in Fig. 18.

So the shift register is remembering whether branches actually were taken or not.

And so you feed that back into the front of the shift register.

You clock data in and out of the shift register with this pin.

A description of how the device could be used as a shift register.